The framework has the following features:

• Low cost: based on general purpose FPGA boards without specific components and interfaces. These low cost boards are even available in the market for development and FPGA evaluation purpose.
• Independence from hardware platform: portable on many FPGA boards.
• Reusability of VHDL components with common functionality-dependent interfaces.
• Exchangeability of sensors, I/O devices and external memory modules thanks to common device class VHDL drivers interfaces.
• Learning and adaptive behaviour concentrated in one or more VHDL Neural Network modules. These new NN paradigms tailored for hardware implementation should be developed inside the project.
• No need of hardware design and fabrication.
• Fast time to market: development of new smart devices needs only design of new application-specific VHDL modules.
• Modularity: more complex systems can be created connecting many FPGA boards.

The project main objective is the definition and design of a framework that could become a standard for the development of smart devices with the following characteristics:
Low cost:
The project is based on available FPGA boards that are normally produced by FPGA core-business companies and third part companies as development/evaluation platforms.
The baseline for the choice of the hardware platform must be the minimal configuration such as the board with one or more FPGA and a (E)PROM for automatic configuration of the FPGA at bootstrap. Anyway the architecture developed in the project is portable on any (note.1) FPGA based board considering that special components eventually built on board should be provided of common interface VHDL drivers for their class as well as external devices.
Also low cost boards have high speed buses and then can be connected in multiple instances distributing complex behaviours on different FPGA and different boards.
Independence from hardware platform:
The development framework that is the core of the project must not be related to any existing board with specific additional behaviours. The development framework must warranty that any application can work on any FPGA (note.1) board or FPGA board system (more boards connected).
Only the change of communication devices and sensors needs the development of new drivers while the main application and basic behaviour modules should not be modified.
Any module should be documented with resource requirements and possibly a list of actually available FPGAs in which it can be implemented.
Reusability of VHDL components:
These components have standard behaviour-dependent interfaces
These are semantic or application related VHDL modules that can perform specific and common sub-tasks (ex: features extraction). These must have a «server» role for the application. These components must have a specific common interface well defined for any kind of specific behaviour (ex: composite profile extraction). The UML «Logical view diagram» shows the concepts of common interface for specific functionality that enables the reusability of components.
Exchangeability of sensors, I/O devices and external memory:
VHDL drivers for sensors, communication ports, and memory must have a defined interface for any specific function/device type (ex: colour CCD camera) and must work as servers.
The UML «Logical view diagram» shows the concept of common interfaces of drivers for specific classes of devices that enables the exchangeability of devices in the same class (see also UML <<Deployment view diagram>>).

(note.1) constraints should be related only to resources (size and architecture dependent) capacity of FPGA and resources requirements of behavioural VHDL modules
 

Learning and adaptive behaviour:
This is concentrated in one or more VHDL Neural Network modules. These new NN paradigms tailored for hardware implementation should be developed inside the project.
These VHDL modules are neural network algorithms tailored for hardware implementation and are the key for the adaptive and learning behaviour of the development framework. Any application of a new smart device should use these «neural engines» to add adaptive and learning capability.
These modules, as any other basic behaviour module in the architecture, work as servers for the application.
An example of these NN is a Radial Basis Function NN tailored for hardware implementation.
Typical Radial Basis Function implementations in hardware have high CLB (Configurable Logic Blocks) consumption and then few neurones (few prototypes) can be realised on actual FPGA.
This paradigm has the same basic behaviour and advantages of RBF NN:

• New learning doesn’t affect previous learning
• Transparent behaviour (doesn’t work as a black-box)
• Computational simplicity

Fast time to market:
The target is a framework with hardware modules that can be easily connected and VHDL modules that can manage sensors, basic behaviours (ex: features extraction, pattern recognition), external memory modules. Having this framework, the development of a new smart device needs only design and synthesis of an application specific VHDL module. This framework must define clearly the interfacing rules of modules enabling people to develop new drivers for new sensors and new implementations of basic behaviour modules.
Development of new basic behaviours or new classes device-drivers needs the definition of interface specifications compliant with the generic interfacing rules of the framework.
An example could be development of drivers for linear cameras and stereovision features extraction modules. In this way the framework would be growing anytime it would be used in a new application field.
 
 

Platform analysis and design:

• Definition of system requirements
• Definition of minimal hardware requirements
• Identification of low cost commercially available FPGA boards from different companies matching the requirements
• Analysis and design of system and it’s components hierarchy
• Definition of standard interfaces for VHDL device class drivers
• Definition of standard interfaces and design of basic behaviour modules
• Analysis and design of NN paradigms tailored for VHDL implementation with minimal resources consumption and definition of standard interfaces for any NN class

• Identification of specific commercially available sensors
• Development of VHDL class drivers for specific sensors following the specifications that are output of the analysis and design step
• Development of VHDL basic behaviours modules following the specifications that are output of the analysis and design step
• Development of VHDL Neural Networks following the specifications that are output of the analysis and design step
• Simulation and test of all VHDL modules

• Identification of a specific target device performing a goal-directed task
• Analysis of the application behaviour and identification of specific sensors and I/O requirements, basic behaviours requirements and neural network typology requirements
• Design of the application behaviour using the Neural Network paradigm, basic behaviour modules and drivers
• Analysis and design of special behavioural requirements as learning facility with connection of the device to a personal computer
• Simulation and test on personal computer of the system

• Development of the VHDL application block implementing the behaviour as described in the specifications that are output of the design step
• Simulation and test on personal computer of the VHDL application block
• Development of software for learning facility on personal computer if required by the analysis and design step
• Hardware resources verification
• Deployment

Due to the interdisciplinarity of the project it is not easy identify a unique «state of the art».
We can identify a «state of the art» in the following fields related with the targets of the project:

• development of a generic VHDL library

• development of a generic VHDL framework with components having common behaviour-related interfaces

• specialisation of the above framework for the development of learning and adaptive devices

• research on neural networks implementation in hardware

1) Industrial standard
2) VHDL library
3) FPGA based devices

End-user should be in one of the following categories:

1) small companies having know-how to design software and hardware but having not resources to produce hardware.  In the last years,  a lot of small software-houses have been able to offer competitive solutions in a market where bigger companies where consolidated. This fact didn’t happen for hardware because the production cost (added anyway to design cost) is a big obstacle for small companies to be competitive in this field. The framework should enable small companies to produce electronic devices

• fast time to market (no hardware production / reuse of basic functionality from HDL library)
• low cost (the hardware supports are commercially available and not custom)
• low investment risk (the hardware supports bought are not related to a specific application)

2) big companies that have enough resources for the production of  hardware but consider a flexible and «fast time to market» solution more adequate for devices characterised by rapid and continuous evolution for growing performances or changing features demand.

Generally, considering the «smart devices» philosophy of the framework (such as devices where intelligence is embedded and hidden at user), those companies should operate principally on automotive, «domotics» and automation. In the first two fields the trend is production of easy-to-use devices with a philosophy completely different from that of personal computer.

In the past years we have seen many small software-house companies realise products that have been competitive with products from big companies. This situation has been possible due to the fact products based only on software requires knowledge and not high investments in hardware resources and instruments. So we have assisted at the birth of many small companies in this field.
In other way we have never seen small companies produce hardware products competitive in the market. The main problem is that hardware production requires investments that goes over the human resources and often some activities are realised in outsourcing. This situation is critical for small companies and often stops their activity in the first years of life.
The rules that enable a small company to survive and be competitive in the market of hardware electronic products are substantially two:

• identify a high technology specialised market
• realise a production framework that enables reutilization of hardware and software components for the major number of products in their market

VHDL is a standard (VHDL-1076) developed by the IEEE. The language has been through a couple of revisions, the most widely used version is the 1987 (Std 1076-1987) version, sometimes referred to as VHDL'87, but also just VHDL. However, there is a newer revision of the language referred to as VHDL'93. VHDL'93 (adopted in 1994 of course) is fairly new and is still in the process of replacing VHDL'87.
The project uses the VHDL standard language and wants to produce a standard framework on top of this language. Really the framework should have rules that enable the implementation virtually in any kind of hardware description language but the real implementation of the framework (the library) is realised using VHDL standard.
The main goal of the project is the creation of an international standard for the design of smart devices that enables reuse of components and exchangeability of hardware reducing production costs.
Actually a generic standard that defines common interfaces for VHDL modules related to specific functionality is missing and normally modules implementing the same functionality have completely different interfaces. The project is oriented to the development of smart devices based on cognitive and neural behaviours but the framework functionality hierarchy is really open to the addition of any new directory related to a different field (as example telecommunication).
A non-monolithic management of the framework library and granularity of IP should help partners of the consortium to apply the work developed inside the project on their own typical market. In this way the project strengthens its vocation to create a «standard» for fast time-to-market development of smart devices instead of a simple VHDL library.