The Consortium is composed by Universities and SMEs in equilibrated number and the expertise of them shows a very high interdisciplinarity.
There are partners with high experience in smart applications design without knowledge of neural networks and VHDL that can support the consortium with their application and algorithmic experience producing specifications for specific applications.
There are partners with strong experience in neural networks design and research. These partners can use their knowledge to produce specifications for the implementation in hardware of the most optimised neural network paradigms.
There are partners with long experience and structures to develop VHDL code under specifications and can produce rules for the optimisation of algorithms for hardware implementation.
 
 
 

DIMI
Department of Mathematics and Computer Science
University of Udine
http://www.dimi.uniud.it/labs/avires/
ITALY (UNI)
Ing. GianLuca Foresti: foresti@dimi.uniud.it
Dr. Christian Micheloni: michelon@dimi.uniud.it
Dr. Snidaro: snidaro@dimi.uniud.it
ORGANISATION AND EXPERTISE:
The Artificial Vision and Real-Time Systems (AVIRES) research group is composed of about 10 members, including a professor, two assistant professors, Ph.D. students, and external cooperating persons. The activities of the group deal with many topics in the areas of Computer Vision, Pattern Recognition and Real-Time Systems. The main sources of its research funding include the European Union (EU), the National Research Council (CNR) of Italy, the Italian Ministry for the University and Research (MURST), and industry. The group has developed close links with industry and research laboratories, including Autostrade, Autovie Venete, Tecnomare, IRST, etc. and also co-operates with many international research institutes. It is in contact with industrial and academic teams involved in joint EU projects (ESPRIT, MAST, CRAFT, etc.) and with foreign universities.The AVIRES research group has specific experience in the development of real-time video-based surveillance systems. In particular, knowledge is available in the context of low-level and high-level image sequence processing techniques aimed at assisting human operators in understanding and interpreting "situations of interest" occurring in variable-complexity monitored scenes. Expertise is in the following fields :

Multisensor image processing

•  Multisensor (range, infrared, optical) image analisys
•  Low-level Image Processing : image acquisition, pre-processing, enhancement and filtering.
•  Change-detection and attention-focusing methods (blob extraction).
•  Linear and non-linear feature extraction and grouping (2D and 3D geometric primitives).
•  Perceptual grouping and image segmentation (edges and regions).

•  Robust feature tracking.
•  Outlier feature detection and rejection.
•  Ego-motion estimation and compensation.
•  Automatic regulation of camera parameters (focus, iris, zoom).
•  3D scene understanding with variable illumination conditions.

•  Spatial and temporal analysis of video sequences.
•  Motion detection and estimation with fixed and mobile camera.
•  Robust object tracking.
•  Shadow detection and elimination.
•  Distributed networks of Extended Kalman Filters.

•  Integration of multisensor data (optical, infrared, radar, etc...)
•  Distributed sensory networks (DSNs)
•  Bayesian Networks.
•  Multilevel Markov Random Fields.

•  Real-time recognition of 2D and 3D objects in real environments.
•  Neural Networks (multilayer perceptron, neural trees, self organizing maps).
•  Decision trees and associative memories.
•  Template matching.

•  Intruder detection
•  Human behaviour analysis and understanding
•  Event detection
•  Real time monitoring of outdoor enviroments (railway stations, airports, motorway, etc...)
•  Face detection and recognition
•  Mobile robot navigation for indoor surveillance.

UWC
Intelligent Systems Laboratory
School of Engineering, Cardiff University  (MEC)
www.mec.cf.ac.uk
UNITED KINGDOM (UNI)
Prof. Pham DT: phamdt@cf.ac.uk
Dr. Yong XU: xuy@cf.ac.uk
Dr. Zuobin Wang: wangz@cf.ac.uk
ORGANISATION AND EXPERTISE:
The award-winning Manufacturing Engineering Centre (MEC) forms part of Cardiff University, which dates back to 1883 and is one of Britain's major civic universities. The 80-strong ISO 9001:2000 accredited Centre has an international reputation for its leading-edge research in advanced manufacturing and information technology spanning a broad spectrum of subjects. Its track record of successful collaboration with industry has culminated in a number of major prizes and awards, including the DTI Secretary of State's first prize and the Queen's Anniversary prize.
The MEC has more than 70 full-time researchers and is currently coordinating several national and European RTD projects including three FP6 projects: 4M (NoE), I-PROMS (NoE) and TAI-CHI (STREP). The ELAN project will receive strong support from the two networks in manufacturing technologies (including micro/nano technologies). In recent years, the MEC has involved in 17 EU projects. The proposed RTD activities will be carried out in the Intelligent Systems Laboratory (ISL) of the MEC.
Qualifications of key personnel assigned to this project:
DUC TRUONG PHAM, BE, PhD, DEng, CEng, FIEE, FREng, OBE, is Professor and Director of the Manufacturing Engineering Centre. His research areas include knowledge-based systems, quality control, visual inspection and system identification and optimisation and control using artificial intelligence. He has more than 200 publications. He is a member of the editorial boards and panels of six international journals and an editor of the Springer-Verlag Advanced Manufacturing book series. Professor Pham is a recipient of several prizes including The Queen’s Prize, and the Sir Joseph Whitworth prize. He is a Fellow of the Royal Academy of Engineering and a Fellow of the Institution of Electrical Engineers.
ZUOBIN WANG, BSc, MSc, PhD, MSPIE, is a senior research associate and project manager of the Intelligent Systems Laboratory in the Manufacturing Engineering Centre. He has been involved in five EC projects since 1997. His research interest is in the areas of electronic devices, applications of microprocessors, signal/image processing, precision measurement and instrumentation including hardware and software design. He has published more than 20 papers. He is a member of SPIE, and was listed in Who’s Who in the World in 2000.
 

UTBM
Laboratoire Systèmes et Transports
Université de Technologie de Belfort-Montbéliard
www.utbm.fr
FRANCE (UNI)
Dr. Yassine Ruichek: Yassine.Ruichek@utbm.fr
ORGANISATION AND EXPERTISE:
Environment perception of intelligent vehicles by stereo vision, using soft-computing techniques as neural networks and genetic algorithms. Multi-agent systems, Modelization and Simulation.
Dr. Yassine Ruicheck published many papers on his researches in the last ten years.
 

ISRATEC
Isratech SRL
www.isratech.ro
ROMANIA (SME)
Dr. Eliahu Friedmann: eli_f@netvision.net.il
ORGANISATION AND EXPERTISE:
Isratech is an ASIC design house with a staff of 50 engineers in the different expertise of the ASIC design specializations. They have teams that can bring a project from an idea to GDSII, through all the industry standard flow.
Isratech was founded in 1997 by Eliahu Friedman. In 1999, Isratech was acquired by Or-Ment Consulting from San Jose, California. Born in Cluj, Romania, educated in Israel, Eliahu is the bridge on the gap between the Western & Romanian working culture.
Isratech employs over 50 skilled engineers. The new employees are tested and trained when employed to ensure that the skill level in electronics and IC design is maintained.
Isratech provides solutions for both Analog and Digital Design, in VHDL or Verilog, CAD/CAE SW development. They also offer Layout, Place and Route and ATPG services.
Expertise is in the following activities :
Front-End :
Design from Specification to RTL
They take customer specifications, encode them in RTL, and synthesize them. They provide static timing clean blocks based on your timing constraints. They also provide the verification suite used to check the code correctness.
Design Verification
JTAG&ATPG insertion
Syntest DFT tools allow us to insert the JTAG and ATPG scan chains at the end of the design cycle, directly into the finished netlist and still meeting the timing and functionality requirements.
Back-End :
Chip Layout
They take the netlist , timing constraints and chip (core) physical details, and provide the gds, timing, DRC and LVS clean.
Circuit design
CAD SW :
ASIC Design Kit
Understanding the ASIC design flow both at the front-end and back-end enable them to write the SW and/or scripts to accomplish those tasks. They can write design kits, containing tech-mappers, place and route, handle test vectors, converters for formats and other utilities.
Neural Networks Design: They have engineers that already made feasibility studies for the implementation in hardware of neural network algorithms.
 

NUBM
North University of Baia Mare
www.ubm.ro
ROMANIA (UNI)
Dr. Stefan Oniga: onigas@ubm.ro
EXPERTISE:
Digital system design with VHDL for programmable logic devices (PLD); digital neural network implementation in PLD.
They have experience in application of neural networks for electronic nose and artificial hands.
 

UOM
Dept. of  Microelectronics
Faculty of Engineering
University of  Malta
http://www.eng.um.edu.mt/microelectronics/microelectronics.html
MALTA (UNI)
Dr. Edward Gatt: ejgatt@eng.um.edu.mt
EXPERTISE:
Implementation of analog neural circuits for voice recognition – VHDL – hardware and software neural networks simulation.
They have realised analog and digital chips based on neural networks algorithms for voice recognition and published many papers on the results.
 

ZTM
Zaklad  Techniki Mikroprocesorowej
www.ztm-exe.com.pl
POLAND (SME)
Dr. Jerzy Brzeski: jb@ztm-exe.com.pl
EXPERTISE:
They are engaged in designs and production of electronic systems basing on microprocessors.
These are equipment both autonomous and working with personal computers.
They also writes software for DOS and Windows including databases service.
ZTM has developed a smart camera for face recognition and fingerprint recognition using algorithms on DSP.
 

SNET
SpikeNet Technology SARL
http://www.spikenet-technology.com
 FRANCE (SME)
Dr. Simon THORPE: thorpe@cerco.ups-tlse.fr
EXPERTISE:
Company Expertise: Real-time Image Processing using large scale networks of spiking neurones.
They have designed a fast and low resource consuming neural network algorithm based on spikes as biological neurones: this is actually one of the most innovative neural network paradigms.
Dr. Thorpe has published many papers on this research in the last ten years on the most important specialised magazines like « Neural Networks » that is the official magazine of « International Neural Network Society »
 

DELTATEC
Deltatec S.r.l
http://www.deltatec.be
BELGIUM (SME)
Christian Dutilleux: c.dutilleux@deltatec.be
ORGANISATION AND EXPERTISE:
Since 1988, Deltatec has been designing FPGAs. With over 14 years of experience, more than 300 designs and a team of 11 experienced engineers, they are a first-rate partner for this first-rate technology. Deltatec is already involved in the RECONF project: RECONF is a project funded by the European Comission through the IST Programme (Contract IST-2001-34016).